IS61QDP2B24M18A Datasheet, PDF (20/31 Pages) Integrated Silicon Solution, Inc – 2Mx36 and 4Mx18 configuration available

IS61QDP2B24M18A/A1/A2
IS61QDP2B22M36A/A1/A2
READ, WRITE, AND NOP TIMING DIAGRAM
1
2
3
4
5
6
7
READ WRITE READ WRITE READ WRITE
tKHKH
WRITE NOP
K Clock
K# Clock
tKHKL
tKHK#H
tAVKH tKHAX
Address
(SA)
A1 A2 A3 A4 A5 A6
A7
tIVKH tKHIX
R#
tIVKH tKHIX
W#
BW_x#
Data-In
(D)
Data-Out
(Q)
QVLD
CQ Clock
B2-1 B2-2 B4-1 B4-2 B6-1 B6-2 B7-1 B7-2
tDVKH
tKHDX
D2-1 D2-2 D4-1 D4-2 D6-1 D6-2 D7-1 D7-2
tCHQX1
Q1-1 _Q1-2 Q1-3 Q1-4 Q3-1
tCHQV
tCHQX
Q3-2
tQVLD
tCQHQV
tCHCQV
tCQHQX
tQVLD
CQ# Clock
tCHCQX
tCHQZ
Undefined
Don’t Care
Notes:
1. If address A1 = A2, data Q1-1 = D2-1 and data Q1-2 = D2-2. Write data is forwarded immediately as read results.
2. B2-1 and B2-2 refer to all BWx# byte controls for D2-1 and D2-2 respectively.
3. B4-1 and B4-2 refer to all BWx# byte controls for D4-1 and D4-2 respectively.
4. B6-1 and B6-2 refer to all BWx# byte controls for D6-1 and D6-2 respectively.
5. B7-1 and B7-2 refer to all BWx# byte controls for D7-1 and D7-2 respectively.
6. Outputs are disabled one cycle after a NOP.
Integrated Silicon Solution, Inc.- www.issi.com
20
Rev. B
02/11/2014