IS42S32400D Datasheet, PDF (20/60 Pages) Integrated Silicon Solution, Inc – 4Meg x 32 128-MBIT SYNCHRONOUS DRAM

IS42S32400D
INITIALIZE AND LOAD MODE REGISTER⁽¹⁾
CLK
T0
tCK
tCKS tCKH
CKE
tCMH tCMS
COMMAND _NOP
T1
tCMH tCMS
PRECHARGE
Tn+1
tCH
tCMH tCMS
AUTO
REFRESH
DQM0-DQM3
To+1
tCL
NOP
AUTO
REFRESH
A0-A9, A11
A10
BA0, BA1
ALL BANKS
SINGLE BANK
ALL BANKS
Tp+1
Tp+2
Tp+3
NOP
Load MODE
REGISTER
NOP
ACTIVE
tAS tAH
CODE
tAS tAH
CODE
tAS tAH
CODE
ROW
ROW
BANK
DQ
T
Power-up: VCC
and CLK stable
T = 100µs Min.
tRP
tRC
Precharge AUTO REFRESH
all banks
tRC
AUTO REFRESH
tMRD
Program MODE REGISTER^{(2, 3, 4)}
DON'T CARE
Notes:
1. If CS is High at clock High time, all commands applied are NOP.
2. The Mode register may be loaded prior to the Auto-Refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after the command is issued.
20
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
03/03/09