IS25WP128 Datasheet, PDF (20/107 Pages) Integrated Silicon Solution, Inc – 1.8V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI

IS25WP128/064/032
EXTENDED READ PARAMETER BITS
Table 6.12 and Table 6.13 define all bits that control features in SPI/QPI modes. The ODS2, ODS1, ODS0
(EB7, EB6, EB5) bits provide a method to set and control driver strength. The five bits (EB4, EB3, EB2, EB1,
EB0) remain reserved for future use.
The SET EXTENDED READ PARAMETERS Operation (SERPNV: 85h, SERPV: 83h) is used to set all the
Extended Read Register bits, and can thereby define the output driver strength used during READ modes.
SRPNV is used to set the non-volatile register and SRPV is used to set the volatile register.
Table 6.12 Extended Read Register Bit Table
EB7
EB6
EB5
ODS2
ODS1
ODS0
Default
1
1
1
EB4
Reserved
1
EB3
Reserved
1
EB2
Reserved
1
EB1
Reserved
1
EB0
Reserved
1
Table 6.13 Extended Read Register Bit Definition
Bit
Name
Definition
EB0
Reserved Reserved
EB1
Reserved Reserved
EB2
Reserved Reserved
EB3
Reserved Reserved
EB4
Reserved Reserved
EB5
ODS0
EB6
ODS1
Output Driver Strength:
Output Drive Strength can be selected according to Table 6.14
EB7
ODS2
Read-
/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Non-Volatile
and Volatile
Table 6.14 Driver Strength Table
ODS2
ODS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
ODS0
0
1
0
1
0
1
0
1
Description
Reserved
12.50%
25%
37.50%
Reserved
75%
100%
50%
Remark
Default
Integrated Silicon Solution, Inc.- www.issi.com
20
Rev. 00B
11/14/2014