IS42S16128 Datasheet, PDF (2/75 Pages) Integrated Silicon Solution, Inc – 128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM

IS42S16128
ISSI ^®
PIN FUNCTIONS
Pin No.
20 to 24,
27 to 30
19
16
34
35
18
2, 3, 5, 6, 8, 9, 11
12, 39, 40, 42, 43,
45, 46, 48, 49
14, 36
17
15
7, 13, 38, 44
1, 25
4, 10, 41, 47
26, 50
Symbol
A0-A8
Type
Input Pin
A9
Input Pin
CAS
Input Pin
CKE
Input Pin
CLK
Input Pin
CS
Input Pin
I/O0 to
I/O15
I/O Pin
Function (In Detail)
A0 to A8 are address inputs. A0-A8 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command
input. A8 is also used to determine the precharge mode during other commands. If
A8 is LOW during precharge command, the bank selected by A9 is precharged, but
if A8 is HIGH, both banks will be precharged.
When A8 is HIGH in read or write command cycle, the precharge starts automati-
cally after the burst access.
These signals become part of the OP CODE during mode register set command
input.
A9 is the bank selection signal. When A9 is LOW, bank 0 is selected and when high,
bank 1 is selected. This signal becomes part of the OP CODE during mode register
set command input.
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.
The CKE input determines whether the CLK input is enabled within the device.
When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when
LOW, invalid. When CKE is LOW, the device will be in either the power-down mode,
the clock suspend mode, or the self refresh mode. The CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM,
UDQM
Input Pin
RAS
Input Pin
WE
Input Pin
VCCQ Power Supply Pin
VCC Power Supply Pin
GNDQ Power Supply Pin
GND Power Supply Pin
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function corre-
sponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the
input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH,
input data is masked and cannot be written to the device.
RAS, in conjunction with CAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.
WE, in conjunction with RAS and CAS, forms the device command. See the
"Command Truth Table" item for details on device commands.
VCCQ is the output buffer power supply.
VCC is the device internal power supply.
GNDQ is the output buffer ground.
GND is the device internal ground.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00