IS61DDB41M18A Datasheet, PDF (19/30 Pages) Integrated Silicon Solution, Inc – 1Mx18, 512Kx36 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

IS61DDB41M18A
IS61DDB451236A
Read, Write, and NOP Timing Diagram
Notes: 1. Q1-0 refers to the output from address A1. Q1-1 refers to the output from the next burst address following A1.
2. Outputs are disabled (high impedance) one clock cycle after a NOP.
3. The NOP cycle is not necessary for correct device operation, however, at high clock frequencies, it might be required to prevent bus contention.
Integrated Silicon Solution, Inc.- www.issi.com
19
Rev. 00A
7/05/2012