IS43R16400B Datasheet, PDF (18/57 Pages) Integrated Silicon Solution, Inc – Four internal banks for concurrent operation

IS43R16400B
AC TIMING REQUIREMENTS
Absolute Specifications (VDD, VDDQ = 2.6 V ± 0.1V (-4), 2.5V ± 0.2V (-5, -6)
PARAMETER
SYMBOL
DQ output access time for CLK,/CLK
DQS output access time for CLK,/CLK
CLK high-level width
CLK low-level width
CLK half period
tAC
tDQSCK
tCH
tCL
tHP
CLK cycle time CL=4
CL=3
CL=2.5
CL=2
DQ and DM input hold time
DQ and DM input setup time
Control & Address input pulse width (for each
input)
DQ and DM input pulse width (for each input)
DQ & DQS high-impedance time from CLK,/CLK
DQ & DQS low--impedance time from CLK,/CLK
DQS--DQ Skew, DQS to last DQ valid, per group,
per access
DQ/DQS output hold time from DQS
Data Hold Skew Factor
Write command to first DQS latching transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
MODE REGISTER SET command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and Control input hold time (fast slew
rate)
Address and Control input setup time (fast slew
rate)
Address and Control input hold time (slow slew
rate)
Address and Control input setup time (slow slew
rate)
Read preamble
Read postamble
ACTIVE to PRECHARGE command
tCK(4)
tCK(3)
tCK(2.5)
tCK(2)
tDH
tDS
tIPW
tDIPW
tHZ
tLZ
tDQSQ
tQH
tQHS
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPRES
tWPST
tWPRE
tIHF
tISF
tIH
tIS
tRPRE
tRPST
tRAS
-6
MIN
-0.7
-0.6
0.45
0.45
min
(tCL,tCH)
–
6
6
7.5
0.45
0.45
2.2
MAX
0.7
0.6
0.55
0.55
–
–
12
12
12
–
–
–
UNITS
ns
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
1.75
–
ns
–
0.7
ns
-0.7
–
ns
–
0.45
ns
tHP-tQHS –
ns
–
0.55
ns
0.75
1.25 tCK
0.35
–
tCK
0.35
–
tCK
0.2
–
tCK
0.2
–
tCK
2
–
tCK
0
–
ns
0.4
0.6
tCK
0.25
–
tCK
0.75
–
ns
0.75
–
ns
0.8
-–
ns
0.8
–
ns
0.9
1.1
tCK
0.4
0.6
tCK
42
120,000 ns
18
Integrated Silicon Solution, Inc.
Rev.B
10/22/2011