IS42S32800J Datasheet, PDF (17/60 Pages) Integrated Silicon Solution, Inc – Internal bank for hiding row access/precharge

IS42S32800J, IS45S32800J
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
Symbol Parameter
-6
—
Clock Cycle Time
6
—
Operating Frequency
166
tcac
CASLatency
3
trcd
Active Command To Read/Write Command Delay Time
3
trac
RAS Latency (trcd + tcac)

CASLatency = 3
6
CASLatency = 2
—
trc
Command Period (REF to REF / ACT to ACT)
10
tras
Command Period (ACT to PRE)
7
trp
Command Period (PRE to ACT)
3
trrd
Command Period (ACT[0] to ACT [1])
2
tccd
Column Command Delay Time
1
(READ, READA, WRIT, WRITA)
tdpl
Input Data To Precharge Command Delay Time
2
tdal
Input Data To Active/Refresh Command Delay Time
5
(During Auto-Precharge)
trbd
Burst Stop Command To Output in HIGH-Z Delay Time CASLatency = 3
3
(Read)
CASLatency = 2
—
twbd
Burst Stop Command To Input in Invalid Delay Time
0
(Write)
trql
Precharge Command To Output in HIGH-Z Delay Time CASLatency = 3
3
(Read)
CASLatency = 2
—
twdl
Precharge Command To Input in Invalid Delay Time
0
(Write)
tpql
Last Output To Auto-Precharge Start Time (Read) CASLatency = 3
-2

CASLatency = 2
—
tqmd
DQM To Output Delay Time (Read)
2
tdmd
DQM To Input Delay Time (Write)
0
tmrd
Mode Register Set To Command Delay Time
2
-7
-75E Units
7
7.5
ns
143
133
MHz
3
2
cycle
3
2
cycle
6
—
cycle
—
4
10
9
cycle
7
5
cycle
3
2
cycle
2
2
cycle
1
1
cycle
2
2
cycle
5
4
cycle
3
—
cycle
—
2
0
0
cycle
3
—
cycle
—
2
0
0
cycle
-2
—
cycle
—
-1
2
2
cycle
0
0
cycle
2
2
cycle
17
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A
8/14/2014