IS61QDP2B21M18A Datasheet, PDF (13/33 Pages) Integrated Silicon Solution, Inc – 512Kx36 and 1Mx18 configuration available

IS61QDP2B21M18A/A1/A2
IS61QDP2B251236A/A1/A2
x36 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
K (t)
K# (t+0.5)
BW₀#
BW₁#
BW₂#
Write Byte 0
L→H
L
H
H
Write Byte 1
L→H
H
L
H
Write Byte 2
L→H
H
H
L
Write Byte 3
L→H
H
H
H
Write All Bytes
L→H
L
L
L
Abort Write
L→H
H
H
H
Write Byte 0
L→H
L
H
H
Write Byte 1
L→H
H
L
H
Write Byte 2
L→H
H
H
L
Write Byte 3
L→H
H
H
H
Write All Bytes
L→H
L
L
L
Abort Write
L→H
H
H
H
BW₃#
H
H
H
L
L
H
H
H
H
L
L
H
D_B
D0-8 (t)
D9-17 (t)
D18-26 (t)
D27-35 (t)
D0-35 (t)
Don't Care
D_B+1
D0-8 (t+0.5)
D9-17 (t+0.5)
D18-26
(t+0.5)
D27-35
(t+0.5)
D0-35 (t+0.5)
Don't Care
Notes:
1. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
Integrated Silicon Solution, Inc.- www.issi.com
13
Rev. B
10/02/2014