IS61DDP2B22M18A Datasheet, PDF (13/31 Pages) Integrated Silicon Solution, Inc – 2Mx18, 1Mx36 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM

IS61DDP2B22M18A/A1/A2
IS61DDP2B21M36A/A1/A2
x18 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
K (t+1.0)
K (t+1.5)
BW₀
BW₁
D_B
D_B+1
Write Byte 0
L→H
L
H
D0-8 (t+4.0)
Write Byte 1
L→H
H
L
D9-17 (t+4.0)
Write All Bytes
L→H
L
L
D0-17 (t+4.0)
Abort Write
L→H
H
H
Don't Care
Write Byte 0
L→H
L
H
D0-8 (t+4.5)
Write Byte 1
L→H
H
L
D9-17 (t+4.5)
Write All Bytes
L→H
L
L
D0-17 (t+4.5)
Abort Write
L→H
H
H
Don't Care
Notes:
1. For all cases, R/W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
x36 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
K (t+1.0)
K (t+1.5)
BW₀
BW₁
BW₂
BW₃
D_B
D_B+1
Write Byte 0
L→H
L
H
H
H
D0-8 (t+4.0)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+4.0)
Write Byte 2
L→H
H
H
L
H
D18-26 (t+4.0)
Write Byte 3
L→H
H
H
H
L
D27-35 (t+4.0)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+4.0)
Abort Write
L→H
H
H
H
H
Don't Care
Write Byte 0
L→H
L
H
H
H
D0-8 (t+4.5)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+4.5)
Write Byte 2
L→H
H
H
L
H
D18-26 (t+4.5)
Write Byte 3
L→H
H
H
H
L
D27-35 (t+4.5)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+4.5)
Abort Write
L→H
H
H
H
H
Don't Care
Notes:
1. For all cases, R/W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
Integrated Silicon Solution, Inc.- www.issi.com
13
Rev. 00A
7/05/2012