IS43R32400D Datasheet, PDF (12/57 Pages) Integrated Silicon Solution, Inc – Four internal banks for concurrent operation

IS43R32400D
EXTENDED MODE REGISTER (EMR) DEFINITION
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional
functions include DLL enable/disable, and output drive strength selection. The Extended Mode Register is
programmed via the MODE REGISTER SET command (with BA1=0 and BA0=1) and will retain the stored information
until it is reprogrammed,or the device loses power. The Extended Mode Register must be loaded when all banks
are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any
subsequent operation. Violating either of these requirements will result in unspecified operation. Reserved states
should not be used, as unknown operation or incompatibility with future versions may result.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power--up initialization, and upon
returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self
Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled a DLL Reset must follow and 200 clock
cycles must occur before any executable command can be issued.
OUTPUT DRIVE STRENGTH (DS)
The normal drive strength for all outputs is specified to be SSTL_2, Class II. This DRAM also supports a weak driver
strength option, intended for lighter load and/or point--to--point environments.
EXTENDED MODE REGISTER DEFINITION
Extended Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus (Ax)
Ext. Mode Reg. (Ex)
Reserved⁽³⁾
Reserved⁽³⁾
0⁽²⁾
A0 DLL
0 Enable
1 Disable
A6 A1 Drive Strength
0 0 Normal
0 1 Weak
1 1 Matched
BA1 BA0 Mode Register Definition
0 0 Program Mode Register
0 1 Program Extended Mode Register
1 0 Reserved
1 1 Reserved
12
NOTES:
1. MSB depends on DDR SDRAM density.
2. A2 must be 0 to provide compatibility with early DDR devices
3. A logic 0 should be programmed to all unused/undefined ad-
dress bits to ensure future compatibility
Integrated Silicon Solution, Inc.
Rev.  A
09/07/2011