IS43LR32160C Datasheet, PDF (12/47 Pages) Integrated Silicon Solution, Inc – 4M x 32Bits x 4Banks Mobile DDR SDRAM

IS43/46LR32160C
Mode Register
The mode register is used to define the specific mode of operation of the Mobile DDR SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency. The mode register is programmed via the LOAD MODE REGISTER command and will retain the
stored information until programmed again, the device goes into deep power-down mode, or the device loses power.
Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency,
and A7-A12 should be set to zero. BA0 and BA1 must be zero to access the mode register.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result in unspecified operation.
Burst Length
Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure
(Mode Register Set Definition). The burst length determines the maximum number of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4, 8 or 16 are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE
command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A8 when the burst
length is set to two; by A2-A8 when the burst length is set to four; by A3-A8 when the burst length is set to eight; and by A4-A8 when the
burst length is set to sixteen. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block.
The programmed burst length applies to both READ and WRITE bursts.
CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
data. The latency can be set to 2, 3 clocks, as shown in Figure (Standard Mode Register Definition).
For CL = 3, if the READ command is registered at clock edge n, then the data will be available at (n + 2 clocks + tAC). For CL = 2, if the
READ command is registered at clock edge n, then the data will be available at (n + 1 clock + tAC).
Figure 8 : CAS Latency (BL=4)
T0
/C LK
CLK
T1
T1n
T2
T2n
T3
T3n T4
T4n
Command
READ
NOP
NOP
NOP
NOP
DQS
1 tCK
tAC
CL = 2
tRPRE
tRPST
DQ
DQS
2 tCK
CL = 3
D OUT
n
D OUT
n+1
tAC
D OUT
n+2
D OUT
n+3
tRPRE
tRPST
DQ
Don ’ t care
D OUT
n
DOUT
n+1
D OUT
n+2
DOUT
n+3
Rev. B | Aug. 2013
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