IS42S16160B-6BL Datasheet, PDF (12/62 Pages) Integrated Silicon Solution, Inc – 256-MBIT SYNCHRONOUS DRAM

IS42S83200B, IS42S16160B
FUNCTIONAL TRUTH TABLE Continued:
Current State
CS RAS CAS WE
Address
Command
Action
Write Recovering H ×
××
×
DESL
Nop, Enter row active after tDPL
LH
H
H
×
NOP
Nop, Enter row active after tDPL
LH
H
L
LH
L
H
×
BA, CA, A10
BST
Nop, Enter row active after tDPL
READ/READA Begin read ⁽⁸⁾
LH
L
L
LL
H
H
LL
H
L
BA, CA, A10
BA, RA
BA, A10
WRIT/ WRITA
ACT
PRE/PALL
Begin new write
ILLEGAL ⁽³⁾
ILLEGAL ⁽³⁾
LL
L
H
×
REF/SELF
ILLEGAL
LL
L
L
OC, BA
MRS
ILLEGAL
Write Recovering H ×
×
×
×
DESL
Nop, Enter precharge after tDPL
with Auto
LH
H
H
×
NOP
Nop, Enter precharge after tDPL
Precharge
LH
H
L
LH
L
H
LH
L
L
LL
H
H
LL
H
L
×
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
BST
READ/READA
WRIT/WRITA
ACT
PRE/PALL
Nop, Enter row active after tDPL
ILLEGAL^(3,8,11)
ILLEGAL ^(3,11)
ILLEGAL ^(3,11)
ILLEGAL ^(3,11)
LL
L
H
×
REF/SELF
ILLEGAL
LL
L
L
OC, BA
MRS
ILLEGAL
Refresh
H×
×
×
×
DESL
Nop, Enter idle after tRC
LH
H
×
×
NOP/BST
Nop, Enter idle after tRC
LH
L
H
BA, CA, A10
READ/READA ILLEGAL
LH
L
L
BA, CA, A10
WRIT/WRITA ILLEGAL
LL
H
H
BA, RA
ACT
ILLEGAL
LL
H
L
BA, A10
PRE/PALL
ILLEGAL
LL
L
H
×
REF/SELF
ILLEGAL
LL
L
L
OC, BA
MRS
ILLEGAL
Mode Register
H×
××
×
DESL
Nop, Enter idle after 2 clocks
Accessing
LH
H
H
×
NOP
Nop, Enter idle after 2 clocks
LH
H
L
×
BST
ILLEGAL
LH
L
×
BA, CA, A10
READ/WRITE ILLEGAL
LL
×
×
BA, RA
ACT/PRE/PALL ILLEGAL
REF/MRS
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will
be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will
be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
07/28/08