IS61WV12816BLL Datasheet, PDF (11/15 Pages) Integrated Silicon Solution, Inc – 128K x 16 HIGH-SPEED CMOS STATIC RAM

IS61WV12816BLL
IS64WV12816BLL
ISSI ^®
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) ^(1,3)
ADDRESS
t WC
ADDRESS 1
t WC
ADDRESS 2
OE
CE _LOW
t SA
WE
UB, LB
DOUT
DIN
t PBW
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t HA
t SA
t PBW
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. C
02/03/06