IS43TR16128C Datasheet, PDF (11/88 Pages) Integrated Silicon Solution, Inc – Programmable CAS Latency

IS43/46TR16128C, IS43/46TR16128CL,
IS43/46TR82560C, IS43/46TR82560CL
2.3.2 Mode Register MR0
The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length,
read burst type, CAS latency, test mode, DLL reset, WR and DLL control for precharge Power-Down, which include
vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting
low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins according to the
following figure.
BA2 BA1 BA0
000
A14-A13
0* ¹
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
PPD
WR
DLL TM CAS Latency RBT CL
BL Mode Register 0
A8
DLL Reset
0
No
1
Yes
A12
DLL Control for
Precharge PD
0 Slow exit (DLL off)
1
Fast exit (DLL on)
BA1 BA0
00
01
10
11
MR Select
MR0
MR1
MR2
MR3
A7 mode
A3 Read Burst Type
A1 A0
0 Nomal
0 Nibble Sequential
00
1
Test
1
Interleave
01
10
Write recovery for autoprecharge
11
A11 A10 A9
WR(cycles)
000
Reserved
A6 A5 A4 A2
001
5 ^*2
0000
010
6 ^*2
0010
011
7 ^*2
0100
100
8 ^*2
0110
101
10 ^*2
1000
110
12 ^*2
1010
111
14 ^*2
1100
1110
BL
8 (Fixed)
BC4 or 8 (on the fly)
BC4 (Fixed)
Reserved
CAS Latency
Reserved
5
6
7
8
9
10
11
0001
0011
0101
0111
1001
1011
1101
1111
12
13
14
Reserved
Reserved
Reserved
Reserved
Reserved
1. A14 and A13 must be programmed to 0 during MRS.
2. WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer:
WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than WRmin. The
programmed WR value is used with tRP to determine tDAL.
3. The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each
frequency
4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table.
Figure 2.3.2 — MR0 Definition
2.3.2.1 Burst Length, Type and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3
as shown in Figure 2.3.2. The ordering of accesses within a burst is determined by the burst length, burst type, and the
starting column address as shown in Table below. The burst length is defined by bits A0-A1. Burst length options include
fixed BC4, fixed BL8, and ‘on the fly’ which allows BC4 or BL8 to be selected coincident with the registration of a Read or
Write command via A12/BC#.
Integrated Silicon Solution, Inc. – www.issi.com –
11
Rev. 00A
12/17/2014