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IS42VM32400G Datasheet, PDF (11/33 Pages) Integrated Silicon Solution, Inc – All pins are compatible with LVCMOS interface
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IS42/45SM/RM/VM32400G
Table4: Command Truth Table
Function
Command Inhinit (NOP)
No Operation (NOP)
Mode Register Set
Extended Mode Register Set
Active (select bank and
activate row)
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge Selected Bank
Burst Stop
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Precharge Power Down Entry
Precharge Down Exit
Clock Suspend Entry
Clock Suspend Exit
Deep Power Down Entry
Deep Power Down Exit
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
L
CKEn /CS /RAS /CAS
X
H
X
X
X
L
H
H
X
L
L
L
X
L
L
L
X
L
L
H
X
L
H
L
X
L
H
L
X
L
H
L
X
L
H
L
X
L
L
H
X
L
L
H
H
L
H
H
H
L
L
L
L
L
L
L
H
X
X
H
L
H
H
H
X
X
L
L
H
H
H
X
X
H
L
H
H
H
X
X
L
L
V
V
H
X
L
L
H
H
H
X
/WE
X
H
L
L
H
H
H
L
L
L
L
L
H
H
X
H
X
H
X
H
X
V
L
DQM
X
X
X
X
X
L/H
L/H
L/H
L/H
X
X
X
X
X
ADDR
A10
X
X
OP CODE
OP CODE
Note
4
4
Bank/Row
Bank/Col
L
5
Bank/Col
H
5
Bank/Col
L
5
Bank/Col
H
5
X
H
Bank
L
X
X
3
X
3
X
X
2
X
X
X
X
X
X
X
X
X
X
6
X
X
Note :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
H: High Level, L: Low Level, X: Don't Care, V: Valid
2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once
tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum
of two NOP commands must be provided during tXSR period.
3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
4. A0-A11 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended
mode register set.
5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read
DQM Latency is 2 CLK.
6. Standard SDRAM parts assign this command sequence as Burst Terminate. For Bat Ram parts, the Burst Terminate command is
assigned to the Deep Power Down function.
Rev. A | Apr. 2012
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