IS61LF102436A Datasheet, PDF (1/20 Pages) Integrated Silicon Solution, Inc – 36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

IS61LF102436A IS61VF102436A
IS61LF204818A IS61VF204818A
1M x 36, 2M x 18
36Mb SYNCHRONOUS FLOW-THROUGH
STATIC RAM
APRIL 2008
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expan-
sion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LF: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%
VF: Vdd 2.5V + 5%, Vddq 2.5V + 5%
• JEDEC 100-Pin TQFP and 165-pin PBGA pack-
ages.
• Lead-free available
DESCRIPTION
The  ISSI  IS61LF/VF102436A and IS61LF/VF204818A
are high-speed, low-power synchronous static RAMs de-
signed to provide burstable, high-performance memory for
communication and networking applications. The IS61LF/
VF102436A is organized as 1,048,476 words by 36 bits.
The IS61LF/VF204818A is organized as 2M-words by 18
bits. Fabricated with ISSI's advanced CMOS technology,
the device integrates a 2-bit burst counter, high-speed
SRAM core, and high-drive capability outputs into a single
monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write en-
able (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.
FAST ACCESS TIME
Symbol
Parameter
tkq
Clock Access Time
tkc
Cycle Time
Frequency
-6.5
-7.5
6.5
7.5
7.5
8.5
133
117
Units
ns
ns
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
1
Rev.  B
04/17/08