IS45S83200C Datasheet, PDF (1/40 Pages) Integrated Silicon Solution, Inc – 256 Mb Single Data Rate Synchronous DRAM

IS45S83200C
IS45S16160C
256 Mb Single Data Rate Synchronous DRAM
APRIL 2009
General Description
IS45S83200C is organized as 4-bank x 8,388,608-word x 8-bit Synchronous DRAM with LVTTL interface and
IS45S16160C is organized as 4-bank x 4,194,304-word x 16-bit. All inputs and outputs are referenced to
the rising edge of CLK. IS45S83200C and IS45S16160C achieve very high speed data rates up to 166MHz, and
are suitable for main memories or graphic memories in computer systems.
Features
- Single 3.3V ±0.3V power supply
- Max. Clock frequency :
- 6:166MHz<3-3-3>/-7:143MHz<3-3-3>/-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- LDQM and UDQM (IS45S16160C)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 8192 refresh cycles /64ms
- LVTTL Interface
- Package
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
Pb-free package is available
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. B
04/02/09