IS45S16400E Datasheet, PDF (1/55 Pages) Integrated Silicon Solution, Inc – 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

IS45S16400E
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
NOVEMBER 2009
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 16ms (A2 grade) or
64ms (A1 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Package:400-mil 54-pin TSOP II
• Lead-free package is available
• Automotive temperature grade:
Option A1: -40^oC to +85^oC
Option A2: -40^oC to +105^oC
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS45S16400E is
organized as 1,048,576 bits x 16-bit x 4-bank for improved
performance.The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VDD
1
DQ0
2
VDDQ
3
DQ1
4
DQ2
5
GNDQ
6
DQ3
7
DQ4
8
VDDQ
9
DQ5
10
DQ6
11
GNDQ
12
DQ7
13
VDD
14
LDQM
15
WE
16
CAS
17
RAS
18
CS
19
BA0
20
BA1
21
A10
22
A0
23
A1
24
A2
25
A3
26
VDD
27
54
GND
53
DQ15
52
GNDQ
51
DQ14
50
DQ13
49
VDDQ
48
DQ12
47
DQ11
46
GNDQ
45
DQ10
44
DQ9
43
VDDQ
42
DQ8
41
GND
40
NC
39
UDQM
38
CLK
37
CKE
36
NC
35
A11
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
28
GND
PIN DESCRIPTIONS
A0-A11
Address Input
BA0, BA1
Bank Select Address
DQ0 to DQ15 Data I/O
CLK
System Clock Input
CKE
CS
RAS
CAS
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM
UDQM
VDD
GND
VDDq
GNDq
NC
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. E
11/09/09