IS43R83200B Datasheet, PDF (1/41 Pages) Integrated Silicon Solution, Inc – 32Mx8, 16Mx16 256Mb DDR Synchronous DRAM

IS43R83200B, IS46R83200B
IS43R16160B, IS46R16160B
32Mx8, 16Mx16
256Mb DDR Synchronous DRAM
AUGUST 2010
FEATURES:
• Vdd =Vddq = 2.5V+0.2V (-5, -6, -75)
• Double data rate architecture; two data transfers
per clock cycle.
• Bidirectional , data strobe (DQS) is transmitted/
received with data
• Differential clock input (CLK and /CLK)
• DLL aligns DQ and DQS transitions with CLK
transitions edges of DQS
• Commands entered on each positive CLK edge;
• Data and data mask referenced to both edges of
DQS
• 4 bank operation controlled by BA0 , BA1
(Bank Address)
• /CAS latency -2.0 / 2.5 / 3.0 (programmable) ;
Burst length -2 / 4 / 8 (programmable)
Burst type -Sequential / Interleave (program-
mable)
• Auto precharge/ All bank precharge controlled
by A10
• 8192 refresh cycles / 64ms (4 banks concurrent
refresh)
• Auto refresh and Self refresh
• Row address A0-12 / Column address A0-9(x8)/
A0-8(x16)
• SSTL_2 Interface
• Package:
66-pin TSOP II (x8 and x16)
60-ball TF-BGA (x16 only)
• Temperature Range:
Commercial (0^oC to +70^oC)
Industrial (-40^oC to +85^oC)
Automotive (-40^oC to +85^oC)
DESCRIPTION:
IS43/46R83200B is a 4-bank x 8,388,608-word x8bit,
IS43/46R16160B is a 4-bank x 4,194,304-word x 16bit
double data rate synchronous DRAM , with SSTL_2
interface. All control and address signals are referenced
to the rising edge of CLK. Input data is registered on
both edges of data strobe, and output data and data
strobe are referenced on both edges of CLK. The device
achieves very high speed clock rate up to 200 MHz.
KEY TIMING PARAMETERS
Parameter
Clk Cycle Time
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
Clk Frequency
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2.5
CAS Latency = 2
-5
5
5
7.5
200
200
133
+0.70
+0.70
+0.75
-6
6
6
7.5
167
167
133
+0.70
+0.70
+0.75
-75 Unit
7.5 ns
7.5 ns
7.5 ns
133 MHz
133 MHz
133 MHz
+0.75 ns
+0.75 ns
+0.75 ns
ADDRESS TABLE
Parameter
32M x 8
Configuration
8M x 8 x 4
banks
Bank Address Pins BA0, BA1
Autoprecharge Pins A10/AP
Row Addresses
A0 – A12
Column Addresses A0 – A9
Refresh Count
8192 / 64ms
16M x 16
4M x 16 x 4
banks
BA0, BA1
A10/AP
A0 – A12
A0 – A8
8192 / 64ms
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
1
Rev. E
08/13/2010