IS43R32400A Datasheet, PDF (1/25 Pages) Integrated Silicon Solution, Inc – 4Meg x 32 128-MBIT DDR SDRAM

IS43R32400A
ISSI^®
4Meg x 32
128-MBIT DDR SDRAM
FEATURES
• Clock Frequency: 200, 166, 100 MHz
• Power supply (VDD and VDDQ): 2.5V
• SSTL 2 interface
• Four internal banks to hide row Pre-charge
and Active operations
• Commands and addresses register on positive
clock edges (CLK)
• Bi-directional Data Strobe signal for data cap-
ture
• Differential clock inputs (CLK and CLK) for
two data accesses per clock cycle
• Data Mask feature for Writes supported
• DLL aligns data I/O and Data Strobe transitions
with clock inputs
• Half-strength and Matched drive strength
options
• Programmable burst length for Read and Write
operations
• Programmable CAS Latency (3, 4, 5 clocks)
• Programmable burst sequence: sequential or
interleaved
• Burst concatenation and truncation supported
for maximum data throughput
• Auto Pre-charge option for each Read or Write
burst
• 4096 refresh cycles every 32ms
• Auto Refresh and Self Refresh Modes
• Pre-charge Power Down and Active Power
Down Modes
• Industrial Temperature Availability
• Lead-free Availability
PRELIMINARY INFORMATION
FEBRUARY 2006
DEVICE OVERVIEW
ISSI’s 128-Mbit DDR SDRAM achieves high-speed
data transfer using pipeline architecture and two data
word accesses per clock cycle. The 134,217,728-bit
memory array is internally organized as four banks of
32M-bit to allow concurrent operations. The pipeline
allows Read and Write burst accesses to be virtually
continuous, with the option to concatenate or truncate
the bursts. The programmable features of burst
length, burst sequence and CAS latency enable
further advantages. The device is available in 32-bit
data word size. Input data is registered on the I/O pins
on both edges of Data Strobe signal(s), while output
data is referenced to both edges of Data Strobe and
both edges of CLK. Commands are registered on the
positive edges of CLK. Auto Refresh, Active Power
Down, and Pre-charge Power Down modes are
enabled by using clock enable (CKE) and other inputs
in an industry-standard sequence. All input and
output voltage levels are compatible with SSTL 2.
IS43R32400A
1M x32x4 Banks
VDD: 2.5V
VDDQ: 2.5V
144-ball BGA
KEY TIMING PARAMETERS
Parameter
-5
-6
Unit
CLK Cycle Time (min.)
CAS Latency = 5
5
6
ns
CAS Latency = 4
5
6
ns
CAS Latency = 3
5
6
ns
CLK Frequency (max.)
CAS Latency = 5
200 166
MHz
CAS Latency = 4
200 166
MHz
CAS Latency = 3
200 166
MHz
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. 00D
02/15/06