IS43DR81280 Datasheet, PDF (1/28 Pages) Integrated Silicon Solution, Inc – 1Gb (x8, x16) DDR2 SDRAM

IS43/46DR81280, IS43/46DR16640
1Gb (x8, x16) DDR2 SDRAM
FEATURES
• Clock frequency up to 533MHz
• 8 internal banks for concurrent operation
• 4‐bit prefetch architecture
• Programmable CAS Latency: 3, 4, 5, 6 and 7
• Programmable Additive Latency: 0, 1, 2, 3, 4, 5
and 6
• Write Latency = Read Latency‐1
• Programmable Burst Sequence: Sequential or
Interleave
• Programmable Burst Length: 4 and 8
• Automatic and Controlled Precharge Command
• Power Down Mode
• Auto Refresh and Self Refresh
• Refresh Interval: 7.8 μs (8192 cycles/64 ms)
• OCD (Off‐Chip Driver Impedance Adjustment)
• ODT (On‐Die Termination)
• Weak Strength Data‐Output Driver Option
PRELIMINARY INFORMATION
MARCH 2010
• Bidirectional differential Data Strobe (Single‐
ended data‐strobe is an optional feature)
• On‐Chip DLL aligns DQ and DQs transitions with
CK transitions
• DQS# can be disabled for single‐ended data
strobe
• Read Data Strobe supported (x8 only)
• Differential clock inputs CK and CK#
• VDD and VDDQ = 1.8V ± 0.1V
• PASR (Partial Array Self Refresh)
• SSTL_18 interface
• tRAS lockout supported
• Operating temperature:
Commercial (T_A = 0°C to +70°C ; T_C = 0°C to 85°C)
Industrial (T_A = ‐40°C to +85°C; T_C = ‐40°C to 95°C)
Automotive, A1 (T_A = ‐40°C to +85°C; T_C = ‐40°C to
95°C)
OPTIONS
• Configuration:
− 128Mx8 (16M x 8 x 8 banks)
− 64Mx16 (8M x 16 x 8 banks)
• Package:
− 60‐ball FBGA for x8
− 84‐ball FBGA for x16
Clock Cycle Timing
Speed Grade
CL‐tRCD‐tRP
tCK (CL=3)
tCK (CL=4)
tCK (CL=5)
‐37C
DDR2‐533C
4‐4‐4
5
3.75
3.75
‐3D
DDR2‐667D
5‐5‐5
5
3.75
3
tCK (CL=6)
3.75
3
tCK (CL=7)
3.75
3
Frequency (max)
266
333
Note: The ‐37C device specification is shown for reference only.
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Precharge Addressing
128Mx8
A0‐A13
A0‐A9
BA0‐BA2
A10
64Mx16
A0‐A12
A0‐A9
BA0‐BA2
A10
‐25E
DDR2‐800E
6‐6‐6
5
3.75
3
2.5
2.5
400
‐25D
DDR2‐800D
5‐5‐5
5
3.75
2.5
2.5
2.5
400
‐19F
DDR2‐1066F
7‐7‐7
5
3.75
3
2.5
1.875
533
Units
tCK
ns
ns
ns
ns
ns
MHz
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. – www.issi.com –
1
Rev. 00A, 3/17/2010