IS43DR32800A Datasheet, PDF (1/41 Pages) Integrated Silicon Solution, Inc – 256Mb DDR2 DRAM

IS43DR32800A, IS43/46DR32801A
8Mx32
256Mb DDR2 DRAM
PRELIMINARY INFORMATION
SEPTEMBER 2010
FEATURES
• Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Double data rate interface: two data transfers
per clock cycle
• Differential data strobe (DQS, DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions
with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, and 6
supported
• Posted CAS and programmable additive latency
(AL) 0, 1, 2, 3, 4, and 5 supported
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength, full and
reduced strength options
• On-die termination (ODT)
DESCRIPTION
ISSI's 256Mb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
The 256Mb DDR2 SDRAM is provided in a wide bus
x32 format, designed to offer a smaller footprint and
support compact designs.
ADDRESS TABLE
Parameter
8M x 32
Standard Page
Size Option
Configuration
2M x 32 x 4 banks
Refresh Count 4K/64ms
Row Addressing A0-A11
Column
Addressing
A0-A8
Bank Addressing BA0, BA1
Precharge
Addressing
A10/AP
8M x 32
Reduced Page
Size Option
2M x 32 x 4 banks
8K/64ms
A0-A12
A0-A7
BA0, BA1
A10/AP
OPTIONS
• Configuration:
8M x 32 (IS43DR32800A Standard Page - 4K
refresh)
8M x 32 (IS43/46DR32801A Reduced Page - 8K
refresh)
• Package: x32: 126 WBGA
• Timing – Cycle time
3.0ns @CL=5, DDR2-667D
3.75ns @CL=4,DDR2-533C
5.0ns @CL=3, DDR2-400B
• Temperature Range:
Commercial (0°C ≤ Tc ≤ 85°C; 0°C ≤ Ta ≤ 70°C)
Industrial (–40°C ≤ Tc ≤ 95°C; –40°C ≤ Ta ≤ 85°C)
Automotive, A1 (–40°C ≤ Tc ≤ 95°C; –40°C ≤ Ta ≤ 85°C)
Automotive, A2 (–40°C ≤ Tc ≤ 105°C; –40°C ≤ Ta ≤ 105°C)
Tc = Case Temp, Ta = Ambient Temp
KEY TIMING PARAMETERS
Speed Grade -37C -5B
tRCD
15 15
tRP
15 15
tRC
60 55
tRAS
45 40
tCK @CL=3
5
5
tCK @CL=4
3.75 5
tCK @CL=5
3.75 5
tCK @CL=6
3.75 5
Copyright © 2010 Integrated Silicon Solution, Inc.All rights reserved.ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev.  00E
09/08/2010