IS43DR00-001 Datasheet, PDF (1/5 Pages) Integrated Silicon Solution, Inc – ISSI DDR2 SDRAM Design Considerations Guide

ISSI DDR2 SDRAM Design Considerations Guide
Introduction
This is a general board design considerations guideline for ISSI DDR2 SDRAM, especially for point to
point applications. Chipset companies may have their own application notes for designing using
DDR2 DRAM. ISSI recommends following the chipset company’s guidelines first.
PCB Layout Guidelines
50–60Ω impedance (ZO) is recommended for all traces. FR-4 is commonly used for the dielectric
material. The board thickness and trace width and thickness should be adjusted to match the
impedance. Trace lengths are also influential, and they should be determined by simulation for each
signal group and verified in test.
In general, ISSI recommends the minimum rules for traces in the board as shown below for the
minimization of crosstalk. These rules are based on the assumption of a signal slew rate of 1V/1ns. In
slower applications, cross-talk generally is not a factor, and closer spacing may be allowed.
1. Signals from the same net group should be routed on the same layer.
2. Signals from Byte group, such as DQS, DM and 8 bits of DQ, must be routed in the same layer
3. The deviation of signal propagation delay is dependent on the timing budget on the application.
The following values in the table are good examples at the start of a design.
Signals on Net
All data, address and command signals
must be followed within this variation.
Between CK and CK#.
Between DQSn and DQS#n
Between one clock pair and another clock
pair, eg) CK/CK# and DQSn/DQS#n
Between signals within byte
group(DQS,DM,8bits of DQ)
Maximum deviation of signal Maximum deviation
propagation difference.
of trace length.
±50ps
±6.635mm(261mil)
±2 ps
±0.254mm (10mil)
±5 ps
±0.635mm(25mil)
±10ps
±1.270mm(50mil)
4. Minimum trace width is 0.13mm (5mil).
5. Intranet spacing, the distance between two adjacent traces within a net, is 0.2mm (7mil).
6. Internet spacing, the distance between the two outermost signals of different signal group is
15mil. The same rule applies between one clock pair and another clock pair.
7. Differential clocks should be routed in parallel and keep the trace length short.
8. Differential clocks must be routed on the same layer and placed on an internal layer minimize the
noise.
9. Keep the internet spacing rule between CKE and CK/CK#