IS42S83200A Datasheet, PDF (1/49 Pages) Integrated Silicon Solution, Inc – 256 Mb Synchronous DRAM

IS42S83200A (4-bank x 8,388,608 - word x 8-bit)
IS42S16160A (4-bank x 4,194,304 - word x 16-bit)
ISSI^®
256 Mb Synchronous DRAM
November 2005
DESCRIPTION
IS42S83200A is a synchronous 256Mb SDRAM and is
organized as 4-bank x 8,388,608-word x 8-bit; and
IS42S16160A is organized as 4-bank x 4,194,304-word x
16-bit. All inputs and outputs are referenced to the rising
edge of CLK.
IS42S83200A and IS42S16160A achieve very
high speed clock rates up to 166MHz, and are
suitable for main memories or graphic
memories in computer systems.
FEATURES
ITEM
tCLK Clock Cycle Time
(Min.)
tRAS Active to Precharge Command Period (Min.)
tRCD Row to ColumnDelay
(Min.)
tAC Access Time from CLK
(Max.)
tRC Ref /Active Command Period
(Min.)
CL=2
CL=3
CL=2
CL=3
IS42S83200A/16160A
-6 -7 ^{-75 Unit}
-
-
10 ns
6
7 7.5 ns
42 45
45 ns
15 20
-
-
20 ns
6 ns
5 5.4 ^{5.4 ns}
60 63 67.5 ^ns
IS42S83200A -
Icc1 Operation Current (Single Bank) (Max.)
- 110 mA
IS42S16160A ₁₃₀ 130
-
mA
Icc6 Self Refresh Current
(Max.) -6,-7,-75
3
3
3
mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency:
-6:166MHz<3-3-3>
-7:143MHz<3-3-3>
-75:133MHz<3-3-3>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (IS42S16160A)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 8192 refresh cycles /64ms(4 banks concurrent refresh)
- LVTTL Interface
- Row address A0-12 /Column address A0-9(x8) / A0-8(x16)
- Package: 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
- Lead-free available
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. D
11/01/05