IS42S16100E Datasheet, PDF (1/82 Pages) Integrated Silicon Solution, Inc – 512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM

IS42S16100E
IS45S16100E
512K Words x 16 Bits x 2 Banks
16Mb SYNCHRONOUS DYNAMIC RAM
SEPTEMBER 2009
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 2048 refresh cycles every 32ms (Com, Ind, A1
grade) or 16ms (A2 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Packages: 400-mil 50-pin TSOP-II and 60-ball
TF-BGA
• Temperature Grades:
Commercial (0^oC to +70^oC)
Industrial (-40^oC to +85^oC)
Automotive A1 (-40^oC to +85^oC)
Automotive A2 (-40^oC to +105^oC)
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42/4516100E is
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD
1
DQ0
2
DQ1
3
GNDQ
4
DQ2
5
DQ3
6
VDDQ
7
DQ4
8
DQ5
9
GNDQ
10
DQ6
11
DQ7
12
VDDQ
13
LDQM
14
WE
15
CAS
16
RAS
17
CS
18
A11
19
A10
20
A0
21
A1
22
A2
23
A3
24
VDD
25
50
GND
49
DQ15
48
DQ14
47
GNDQ
46
DQ13
45
DQ12
44
VDDQ
43
DQ11
42
DQ10
41
GNDQ
40
DQ9
39
DQ8
38
VDDQ
37
NC
36
UDQM
35
CLK
34
CKE
33
NC
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
GND
PIN DESCRIPTIONS
A0-A10
Row Address Input
A11
Bank Select Address
A0-A7
Column Address Input
DQ0 to DQ15 Data DQ
CLK
System Clock Input
CKE
CS
RAS
Clock Enable
Chip Select
Row Address Strobe Command
CAS
WE
LDQM
UDQM
VDD
GND
VDDQ
GNDQ
NC
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. D
08/24/09