IS42S16100 Datasheet, PDF (1/78 Pages) Integrated Silicon Solution, Inc – 512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM

IS42S16100
ISSI^®
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
NOVEMBER 2001
FEATURES
• Clock frequency: 166, 143, 100 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank
select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 4096 refresh cycles every 128 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Package 400-mil 50-pin TSOP II
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42S16100 is
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VCC
1
I/O0
2
I/O1
3
GNDQ
4
I/O2
5
I/O3
6
VCCQ
7
I/O4
8
I/O5
9
GNDQ
10
I/O6
11
I/O7
12
VCCQ
13
LDQM
14
WE
15
CAS
16
RAS
17
CS
18
A11
19
A10
20
A0
21
A1
22
A2
23
A3
24
VCC
25
50
GND
49
I/O15
48
I/O14
47
GNDQ
46
I/O13
45
I/O12
44
VCCQ
43
I/O11
42
I/O10
41
GNDQ
40
I/O9
39
I/O8
38
VCCQ
37
NC
36
UDQM
35
CLK
34
CKE
33
NC
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
GND
PIN DESCRIPTIONS
A0-A11
A0-A10
A11
A0-A7
I/O0 to I/O15
CLK
CKE
CS
RAS
Address Input
Row Address Input
Bank Select Address
Column Address Input
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
CAS
WE
LDQM
UDQM
Vcc
GND
VccQ
GNDQ
NC
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. C
11/01/01