IS41LV32256 Datasheet, PDF (1/19 Pages) Integrated Silicon Solution, Inc – 256K x 32 (8-Mbit) EDO DYNAMIC RAM 3.3V, 100/83/66 MHz

IS41LV32256
256K x 32 (8-Mbit) EDO DYNAMIC RAM
3.3V, 100/83/66 MHz
ISSI^®
SEPTEMBER 2000
FEATURES
• 262,144-word by 32-bit organization
• Single +3.3V ± 0.3V power supply
• Four CAS inputs for Byte Write and Byte Read
control
• Refresh modes: RAS-Only, CAS-Before-RAS (CBR),
and Hidden
• 512-cycle refresh in 8 ms
• Fast Page Mode with Extended Data Out
• 100-pin PQFP, TQFP package
DESCRIPTION
The ISSI IS41LV32256 is organized in a 262,122 x 32-bit
CMOS Dynamic Random Access Memory. Four CAS signals
facilitate execution of Byte Read and Byte Write operations.
A very fast EDO cycle time of 10 ns allows an operating
frequency of 100 MHz and makes the IS41LV32256 an ideal
frame buffer memory for graphics applications.
The IS41LV32256 is compatible with JEDEC standard
SGRAMs. This 8-Mbit EDO memory offers a significantly
lower latency and a faster memory cycle than the SGRAM.
ISSI's IS41LV32256 3.3V 256K x 32 device is pin/voltage
compatible with all standard SGRAM parts.
The IS41LV32256 is available in a 100-pin PQFP and TQFP
package.
KEY TIMING PARAMETERS
Parameter
-28
-30
-35 Unit
Max. RAS Access Time (tRAC)
Max. CAS Access Time (tCAC)
28
30
35
ns
9
9
10
ns
Max. Column Address Access Time (tAA) 15
16
18
ns
Max. OE Access Time (tOE)
9
9
10
ns
Min. Read/Write Cycle Time (tRC)
48
53
60
ns
Min. EDO Cycle Time (tPC)
12
12
15
ns
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
1
Rev. A
09/29/00