IS41C16128 Datasheet, PDF (1/21 Pages) Integrated Silicon Solution, Inc – 128K x 16 (2-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

IS41C16128
IS41C16128
128K x 16 (2-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
ISS^ISI^SI®®
AUGUST 1998
FEATURES
• Extended Data-Out (EDO) Page Mode
access cycle
• TTL compatible inputs and outputs
• Refresh Interval: 512 cycles/8 ms
• Refresh Mode : RAS-Only, CAS-before-RAS
(CBR), and Hidden
• JEDEC standard pinout
• Single +5V ± 10% power supply
• Byte Write and Byte Read operation via two CAS
• Available in 40-pin SOJ and TSOP (Type II)
• Industrial temperature available
DESCRIPTION
The ISSI IS41C16128 is a 131,072 x 16-bit high-performance
CMOS Dynamic Random Access Memory. The IS41C16128
offers an accelerated cycle access called EDO Page Mode.
EDO Page Mode allows 256 random accesses within a
single row with access cycle time as short as 12 ns per 16-
bit word. The Byte Write control, of upper and lower byte,
makes the IS41C16128 ideal for use in 16-, 32-bit wide data
bus systems.
These features make the IS41C16128 ideally suited for
high band-width graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The IS41C16128 is packaged in a 40-pin 400-mil SOJ and
TSOP (Type II).
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
CLOCK
GENERATOR
CAS
WE
CONTROL
LOGICS
WE
OE
CONTROL
LOGIC
RAS
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
I/O0-I/O15
A0-A8
ADDRESS
BUFFERS
MEMORY ARRAY
131,072 x 16
This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We
assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
1
PRELIMINARY DR002-1D
08/20/98