IS24L128 Datasheet, PDF (1/15 Pages) Integrated Silicon Solution, Inc – 128K-bit/ 256K-bit 2-WIRE SERIAL CMOS EEPROM

IS24L128
IS24L256
ISSI^®
128K-bit/ 256K-bit
2-WIRE SERIAL CMOS EEPROM
ADVANCED INFORMATION
APRIL 2006
FEATURES
• Two-Wire Serial Interface, I²C^TM compatible
–Bi-directional data transfer protocol
• Low Voltage and Standard Voltage Operation
–Vcc = 1.8V to 3.6V
• 400 KHz (1.8V) and 1 MHz (2.5V, 2.7V, 3.6V)
compatibility
• Low Power CMOS Technology
–Active Current less than 3 mA (3.6V)
–Stanby Current less than 3 µA (3.6V)
–Standby Current less than 1 µA (1.8V)
• Hardware Data Protection
–Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
–5 ms max @ 1.8V
• Organization:
IS24L128–16Kx8 (256 pages of 64 bytes)
IS24L256–32Kx8 (512 pages of 64 bytes)
• 64 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 40 Years
• Industrial temperature range
• 8-pin PDIP, 8-pin (JEDEC) SOIC, and 8-pin
(EIAJ) SOIC packages
• Lead-free available
DESCRIPTION
The IS24L128 and IS24L256 are electrically erasable
PROM devices that use the standard 2-wire interface
for communications. The IS24L128 and IS24CL256
contain a memory array of 128K-bits (16K x 8) and
256K-bits (32 x 8), respectively. Each device is
organized into 64 byte pages for page write mode.
This EEPROM operates in a voltage range of 1.8V to
3.6V for low voltage and standard voltage application
levels. ISSI designed this device family to be a
practical, low-power 2-wire EEPROM solution. The
devices are available in 8-pin PDIP, 8-pin (JEDEC)
SOIC, and 8-pin (EIAJ) SOIC packages.
The IS24L128/256 maintains compatibility with the
popular 2-wire bus protocol, so it is easy to design into
applications implementing this bus type. The simple
bus consists of the Serial Clock wire (SCL) and the
Serial Data wire (SDA). Using the bus, a Master device
such as a microcontroller is usually connected to one
or more Slave devices such as the IS24L128/256. The
bit stream over the SDA line includes a series of bytes,
which identifies a particular Slave device, an
instruction, an address within that Slave device, and a
series of data, if appropriate. The IS24L128/256 has a
Write Protect pin (WP) to allow blocking of any write
instruction transmitted over the bus.
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
ADVANCEDINFORMATION Rev. 00B
03/21/06