62LV12816 Datasheet, PDF (1/9 Pages) Integrated Silicon Solution, Inc – 128K x 16 CMOS STATIC RAM

IS62LV12816L
IS62LV12816L
128K x 16 CMOS STATIC RAM
ISS^ISSI^I®®
ADVANCE INFORMATION
AUGUST 1998
FEATURES
• High-speed access time: 70, 100, and 120 ns
• CMOS low power operation
– 120 mW (typical) operating
– 6 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 3V ± 10% VCC power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA
FUNCTIONAL BLOCK DIAGRAM
1
DESCRIPTION
2 ^{The ISSI IS62LV12816L is a high-speed, 2,097,152-bit static}
RAM organized as 131,072 words by 16 bits. It is fabricated
using ISSI's high-performance CMOS technology. This highly
reliable process coupled with innovative circuit design
techniques, yields high-performance and low power
consumption devices.
3
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down
4 ^{with CMOS input levels.}
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
5 ^{A data byte allows Upper Byte (UB) and Lower Byte (LB)}
access.
The IS62LV12816L is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA.
6
7
A0-A16
DECODER
128K x 16
MEMORY ARRAY
8
VCC
GND
9
I/O0-I/O7
Lower Byte
I/O
DATA
COLUMN I/O
10
I/O8-I/O15
CIRCUIT
Upper Byte
11
CE
OE
WE
CONTROL
CIRCUIT
12
UB
LB
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
1
ADVANCE INFORMATION SR002-0C
08/20/98