AUIRFR5410 Datasheet, PDF (8/12 Pages) International Rectifier – Advanced Planar Technology

AUIRFR5410
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
‚
-
+
ƒ
Circuit Layout Considerations
 Low Stray Inductance
Ground Plane
Low Leakage Inductance
-
Current Transformer
„
-
+

R_G
V_GS
dv/dt controlled by R_G
I_SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
+
-
V_DD
* Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[
] ***
V_GS=10V
D.U.T. I_SD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V_DS Waveform _{Diode Recovery}
dv/dt
Re-Applied
Voltage
Body Diode
Inductor Curent
Forward Drop
Ripple  5%
V_DD
[]
I_SD
[]
*** V_GS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For P-Channel HEXFETS
8
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