AUIRF1324WL Datasheet, PDF (8/11 Pages) International Rectifier – Advanced Process Technology Ultra Low On-Resistance

AUIRF1324WL
+
‚
-

R_G
D.U.T
+
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
ƒ
Circuit Layout Considerations
 Low Stray Inductance
Ground Plane
-
Low Leakage Inductance
Current Transformer
-^„ +
D.U.T. I_SD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V_DS Waveform _{Diode Recovery}
dv/dt
dv/dt controlled by R_G
Driver same type as D.U.T.
V_DD
+
I_SD controlled by Duty Factor "D"
-
D.U.T. - Device Under Test
Re-Applied
Voltage
Body Diode
I_In_nd_du_uc_ct_to_or_{r C}C_uu_rr_ere_nn_t t
Forward Drop
Ripple  5%
* V_GS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET^® Power MOSFETs
* V_GS=10V
V_DD
I_SD
V_(BR)DSS
15V
tp
VDS
L
DRIVER
RG
20V
tp
D.U.T
I_AS
0.01
+
- ^VDD
A
Fig 22a. Unclamped Inductive Test Circuit
LD
VDS
+
VDD -
D.U.T
VGS
Second Pulse Width < 1μs
Duty Factor < 0.1%
Fig 23a. Switching Time Test Circuit
I_AS
Fig 22b. Unclamped Inductive Waveforms
V_GS
90%
10%
V_DS
t_{d(off) tf}
t_{d(on) tr}
Fig 23b. Switching Time Waveforms
L
VCC
DUT
0
210KK
S
Id
Vgs
Vds
Vgs(th)
Fig 24a. Gate Charge Test Circuit
8
Qgodr
Qgd Qgs2 Qgs1
Fig 24b. Gate Charge Waveform
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