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| IRFS4310ZTRLPBF Datasheet, PDF (7/11 Pages) International Rectifier – High Efficiency Synchronous Rectification in SMPS | |||
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IRFB/S/SL4310ZPbF
D.U.T
+
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
+
Â
-
Â
RG
Â
Circuit Layout Considerations
ï ï ï ï·ï Low Stray Inductance
ï ï·ï ï Ground Plane
-
ï ï·ï ï Low Leakage Inductance
Current Transformer
D.U.T. ISD Waveform
Reverse
-Â +
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
*
ï·ï ï dv/dt controlled by RG
ï·ï ï Driver same type as D.U.T.
VDD
Re-Applied
** + Voltage
Body Diode Forward Drop
ï·ï ï ISD controlled by Duty Factor "D"
-
ï·ï ï D.U.T. - Device Under Test
Inductor Curent
Ripple ï£ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
V*G*S*=10V
VDD
ISD
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
VDS
L
DRIVER
RG
2V0GVS
tp
D.U.T
IAS
0.01ï
+
- VDD
A
Fig 22a. Unclamped Inductive Test Circuit
IAS
Fig 22b. Unclamped Inductive Waveforms
VDS
VGS
RG
RD
D.U.T.
10V
Pulse Width ï£ï ï±ï µs
Duty Factor ï£ï ï°ï®ï±ï ï¥
+-VDD
Fig 23a. Switching Time Test Circuit
L
VCC
DUT
0
210K
S
VDS
90%
10%
VGS
td(on) tr
td(off) tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
Vgs(th)
Fig 24a. Gate Charge Test Circuit
www.irf.com
Qgodr
Qgd Qgs2 Qgs1
Fig 24b. Gate Charge Waveform
7
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