IRU1015 Datasheet, PDF (6/8 Pages) International Rectifier – 1.5A LOW DROPOUT POSITIVE ADJUSTABLE REGULATOR

IRU1015
V _ESR
V _ESL
T
LOAD
CURRENT
V_C
1015plt1-1.0
2) With the output capacitance being 1500µF:
∆Vc =
∆t × ∆I
C
=
2 × 1.2
1500
= 1.6mV
Where:
∆t = 2µs is the regulator response time
To set the output voltage, we need to select R1 and R2:
LOAD CURRENT RISE TIME
Figure 5 - Typical regulator response to the
fast load current step
3) Assuming R1 = 121Ω, 1%
R2 =o^VVOREUFT - 1p× 121 =o^31..4255 - 1p× 121 = 213Ω
An example of a regulator design to meet the AMD speci-
fication for 486DX4-120MHz is given below.
Assume the specification for the processor as shown in
Table 1:
Type of
Processor
AMD 486DX4
Vout
Nominal
3.45 V
Imax
1.2 A
Max Allowed
Output Tolerance
±150 mV
Table 1 - GTL+ specification for Pentium Pro
The first step is to select the voltage step allowed in the
output due to the output capacitor’s ESR:
1) Assuming the regulator’s initial accuracy plus the re-
sistor divider tolerance is ≈ ±86mV (±2.5% of 3.45V
nominal), then the total step allowed for the ESR and
the ESL, is -64mV.
Select R2 = 215Ω, 1%
Selecting both R1 and R2 resistors to be 1% toler-
ance results in the least amount of error introduced
by the resistor dividers leaving a ≈ ±2.5% error bud-
get for the IRU1015 reference which is well within the
initial accuracy of the device.
Finally, the input capacitor is selected as follows:
4) Assuming that the input voltage can drop 150mV be-
fore the main power supply responds, and that the
main power supply response time is ≈ 50ms, then
the minimum input capacitance for a 1.2A load step
is given by:
CIN
=
1.2 × 50
0.15
= 400µF
Assuming that the ESL drop is -10mV, the remaining
ESR step will be -54mV. Therefore the output ca-
pacitor ESR must be:
ESR
≤
54
1.2
= 45mΩ
The Sanyo MVGX series is a good choice to achieve
both price and performance goals. The 6MV1500GX,
1500µF, 6.3V has an ESR of less than 36mΩ typi-
cal. Selecting a single capacitor achieves our design
goal.
The ESR should be less than:
ESR
=
(VIN
-
VOUT -
∆I
∆V
-
VDROP)
Where:
VDROP L Input voltage drop allowed in step 4
∆V L Maximum regulator dropout voltage
∆I L Load current step
ESR
=
(5
-
3.45
- 1.2
1.2
-
0.15)
=
0.167Ω
The next step is to calculate the drop due to the ca-
pacitance discharge and make sure that this drop in
voltage is less than the selected ESL drop in the
previous step.
Select a single 1500µF the same type as the output
capacitors exceeds our requirements.Figure 6 shows
the completed schematic for our example.
6
Rev. 1.1
06/29/01