IR3500A Datasheet, PDF (6/48 Pages) International Rectifier – XPHASE3TM VR11.0 & AMD PVID CONTROL IC

IR3500A
PARAMETER
TEST CONDITION
MIN
VDRP Buffer Amplifier
Input Offset Voltage
V(VDRP) – V(IIN), 0.5V ≤ V(IIN) ≤ 3.3V
-5
Source Current
0.5V ≤ V(IIN) ≤ 3.3V
2
Sink Current
0.5V ≤ V(IIN) ≤ 3.3V
0.2
Unity Gain Bandwidth
Note 1
Slew Rate
Note 1
IIN Bias Current
-1
PGOOD Output
Output Voltage
I(PGOOD) = 4mA
Leakage Current
V(PGOOD) = 5.5V
Under Voltage Threshold-VO
decreasing
Reference to VDAC
-380
Under Voltage Threshold-VO
increasing
Reference to VDAC
-315
Under Voltage Threshold
25
Hysteresis
VCCL_DRV Activation
Threshold
I(PG)=4mA, V(PG)<300mV, V(VCCL)=0
1
Open Sense Line Detection
Sense Line Detection Active
150
Comparator Threshold Voltage
Sense Line Detection Active V(VO) < [V(VOSEN+) – V(LGND)] / 2
35
Comparator Offset Voltage
VOSEN+ Open Sense Line
Compare to V(VCCL)
87.5
Comparator Threshold
VOSEN- Open Sense Line
0.36
Comparator Threshold
Sense Line Detection Source V(VO) = 100mV
200
Currents
VRHOT Comparator
Threshold Voltage
1.584
HOTSET Bias Current
-1
Hysteresis
75
Output Voltage
I(VRHOT) = 30mA
VRHOT Leakage Current
V(VRHOT) = 5.5V
VCCL Regulator Amplifier
Reference Feedback Voltage
1.15
VCCLFB Bias Current
-1
VCCLDRV Sink Current
10
UVLO Start Threshold
Compare to V(VCCL)
91
UVLO Stop Threshold
Compare to V(VCCL)
83
Hysteresis
Compare to V(VCCL)
7
General
VCCL Supply Current
3.0
Note 1: Guaranteed by design, but not tested in production
Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offset errors
Note 3: See VIDSEL Functionality Table
TYP
3
0.4
8
4.7
0
150
0
-330
-265
60
2
200
60
90.0
0.40
500
1.600
0
100
150
0
1.19
0
30
93
87
8.25
6.5
MAX
11
30
0.6
1
300
10
-280
-215
95
3.6
250
85
92.5
0.44
700
1.616
1
125
400
10
1.23
1
99
91
9.5
10.0
UNIT
mV
mA
mA
MHz
V/µs
µA
mV
µA
mV
mV
mV
V
mV
mV
%
V
uA
V
µA
mV
mV
µA
V
uA
mA
%
%
%
mA
Page 6 of 48
July 28, 2009