IRU3146 Datasheet, PDF (5/30 Pages) International Rectifier – DUAL SYNCHRONOUS PWM CONTROLLER WITH CURRENT SHARING CIRCUITRY AND AUTO-RESTART

IRU3146
PIN DESCRIPTIONS
PIN#
26
27
28
PIN SYMBOL
VP2
VREF
Gnd
PIN DESCRIPTION
Non-inverting input to the second error amplifier. In the current sharing mode, it is con-
nected to the programming resistor. In independent 2-channel mode it is connected to
VREF pin when Fb2 is connected to the resistor divider to set the output voltage.
Reference Voltage. The drive capability of this pin is about 2uA.
Analog ground for internal reference and control circuitry. Connect to PGnd plane with a
short trace.
1) These pins should not go negative (-0.5V), this may cause instability for the gate drive circuits. To prevent this,
a low forward voltage drop diode is required between these pins and ground as shown in Figure 1.
BLOCK DIAGRAM
Vcc ²
SS2 / SD 8
SS1 / SD 20
25uA 25uA
64uA
Max
64uA
POR
Error Amp1
0.8V
Fb1 22
Comp1 21
Rt 4
Sync 24
VREF 27
VP2 26
0.8V
Error Amp2
Fb2 6
Comp2 7
VSEN1 ²³
VSEN2 5
Gnd 28
Mode
Bias
Generator
3V
0.8V
VP2
0.8V
Mode
Control
VcH1
VcH2
4.2V / 4.0V
3.5V / 3.3V
3.5V / 3.3V
PWM Comp1
UVLO ^POR
0.3V
Thermal
Shutdown
SS1
R
SS1
3uA
Q
Ramp1
Ramp2
Two Phase
Oscillator
Set1 _S
Reset Dom
Set2
Reset Dom
S
PWM Comp2
Q
SS1
SS2
Hiccup
Control
R
Mode
0.3V
SS2
SS2
PGood / OVP
OVP
HDrv OFF / LDrv ON
3uA
Regulator
POR
Mode
20uA
20uA
18 VcH1
17 HDrv1
14 VCL
15 _LDrv1
16 PGnd1
19 OCSet1
10 VcH2
11 HDrv2
25 Hiccup
13 LDrv2
12 PGnd2
9 OCSet2
1 PGood
3 VOUT3
Figure 3 - Block diagram of IRU3146.
Rev. 1.1
6/25/04
www.irf.com
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