IRF9332PBF_15 Datasheet, PDF (5/8 Pages) International Rectifier – Industry-Standard SO-8 Package

50
ID = -9.8A
40
30
20
TJ = 125°C
10
TJ = 25°C
0
0
5
10
15
20
25
-VGS, Gate -to -Source Voltage (V)
Fig 12. On-Resistance vs. Gate Voltage
500
ID
TOP -2.0A
400
-2.8A
BOTTOM -7.8A
300
200
100
0
25
50
75
100 125 150
Starting TJ , Junction Temperature (°C)
Fig 14. Maximum Avalanche Energy vs. Drain Current
IRF9332PbF
50
40
Vgs = -4.5V
30
20
10
Vgs = -10V
0
0 10 20 30 40 50 60 70 80
-ID, Drain Current (A)
Fig 13. Typical On-Resistance vs. Drain Current
1000
800
600
400
200
0
1E-5
1E-4
1E-3
1E-2
1E-1
Time (sec)
Fig 15. Typical Power vs. Time
1E+0
D.U.T * ₊
ƒ
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
-
• Low Leakage Inductance
+
Current Transformer
‚
-
-^„ +

R_G
• di/dt controlled by R_G
• Driver same type as D.U.T.
V_DD
+
• I_SD controlled by Duty Factor "D"
-
• D.U.T. - Device Under Test
* Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
* V_GS=10V
D.U.T. I_SD Waveform
Reverse
Recovery
Body Diode Forward
Current
Current
di/dt
D.U.T. V_DS Waveform
Diode Recovery
dv/dt
V_DD
Re-Applied
Voltage
Body Diode
IInndduuccttoorr CCuurrernetnt
Forward Drop
Ripple ≤ 5%
I_SD
* V_GS = 5V for Logic Level Devices
Fig 16. Diode Reverse Recovery Test Circuit for P-Channel HEXFET^® Power MOSFETs
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