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IR3894M_15 Datasheet, PDF (32/45 Pages) International Rectifier – Single‐Input Voltage, Synchronous Buck Regulator
12A Highly Integrated SupIRBuck
Single‐Input V-o3l2ta-g` e, Synchronous Buck Regulator
PD‐97745
IR3894
ZIN
VOUT
C4
R4 R5
C2
R3 C3
Zf
Gain (dB)
Fb
R6
VREF
E/A
Ve
Comp
|H(s)| dB
FZ1
FZ 2
FP2
F Frequency
P3
Figure 27: Type III Compensation network
and its asymptotic gain plot
Again, the transfer function is given by:
Ve
Vout

H
( s)


Zf
Z IN
By replacing Zin and Zf, according to Fig. 27, the transfer
function can be expressed as:
H (s) 

(1  sR3C3 ) 1  sC 4  R4  R5 
sR5 (C2

C3 )
1


sR3



C2
C2
*

C3
C3



(1

sR4C4
)
                                    ( 2 7 )
The compensation network has three poles and two
zeros and they are expressed as follows:
FP1  0(28)
FP2

2
1
* R4
*C4 (29)
FP3

2
*
R3
1



C2
C2
* C3
 C3




2
*
1
R3
* C2
(30)
FZ 1

2
*
1
R3
*C3 (31)
FZ 2

2
* C4
1
* (R4

R5 )

2
1
* C4
*
R5
(32)
Cross over frequency is expressed as:
Fo

R3
*C4
* Vin
Vosc
*
2
1
* Lo
*Co
(33)
Based on the frequency of the zero generated by the output
capacitor and its ESR, relative to crossover frequency, the
compensation type can be different. Table 3 shows the
compensation types for relative locations of the crossover
frequency.
TABLE 3: DIFFERENT TYPES OF COMPENSATORS
Compensator
Type
Type II
Type III
FESR vs FO
FLC < FESR < FO < FS/2
FLC < FO < FESR
Typical Output
Capacitor
Electrolytic
SP Cap, Ceramic
The higher the crossover frequency is, the potentially faster
the load transient response will be. However, the crossover
frequency should be low enough to allow attenuation of
switching noise. Typically, the control loop bandwidth or
crossover frequency (Fo) is selected such that:
Fo  1/5 ~ 1/10 * Fs
The DC gain should be large enough to provide high
DC‐regulation accuracy. The phase margin should be greater
than 45o for overall stability.
For this design we have:
Vin=12V
Vo=1.2V
Vosc=1.8V (This is a function of Vin, pls. see feed forward
section)
Vref=0.5V
Lo=0.51uH
Co=8x22uF, ESR≈3mΩ each
It must be noted here that the value of the capacitance used
in the compensator design must be the small signal value.
For instance, the small signal capacitance of the 22uf capacitor
used in this design is 10uf at 1.2 V dc bias and 600 kHz frequency. It
is this value that must be used for all computations related to the
compensation.
32 JANUARY 18, 2013 | DATA SHEET | Rev 3.4