IR3837MPBF Datasheet, PDF (31/36 Pages) International Rectifier – HIGHLY INTEGRATED 14A SINGLE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR

IR3837MPbF
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with less than expected results.
Make all the connections for the power
components in the top layer with wide, copper
filled areas or polygons. In general, it is desirable
to make proper use of power planes and
polygons for power distribution and heat
dissipation.
The inductor, output capacitors and the IR3837
should be as close to each other as possible.
This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor directly at
the PVin pin of IR3837.
The feedback part of the system should be kept
away from the inductor and other noise sources.
The critical bypass components such as
capacitors for Vin, Vcc, Vref and Vp should be
close to their respective pins. It is important to
place the feedback components including
feedback resistors and compensation
components close to Fb and Comp pins.
The connection between the OCSet resistor and
the SW pin should not share any trace with the
connection between the bootstrap capacitor and
Vin _PGnd ^{the SW pin. Instead, it is recommended to use a}
Kelvin connection of the trace from the OCSet
rceaspiastco_{Vitrion r}
and the trace
at the SW pin.
from the
P_AG_lsn_od_{, place}
bootstrap
the OCset
AGnd Vout resistor close to the device.
In a multilayer PCB use one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are
referenced. The goal is to localize the high
cAuGrnrednt path to a separate^Volo^uo^t p that does not
interfere with the more sensitive analog control
function. These two grounds must be connected
together on the PC board layout at a single point.
It is recommended to place all the compensation
parts over the analog ground plane in top layer.
The Power QFN is a thermally enhanced
package. Based on thermal performance it is
recommended to use at least a 4-layers PCB. To
effectively remove heat from the device the
exposed pad should be connected to the ground
plane using vias. Figure 30 illustrates the
implementation of the layout guidelines outlined
above, on the IRDC3837 4 layer demoboard.
AGnd
Compensation parts
should be placed as
close as possible to
the Comp pin.
Resistors Rt and
R_OCSet should be
placed as close as
possible to their pins.
PGnd
Vin
Vout
PGnd
Enough copper &
minimum length
ground path between
Input and Output
All bypass caps
should be placed as
close as possible to
their connecting
pins.
Fig. 30a. IRDC3837 Demoboard layout
considerations – Top Layer
Rev 1.31
31