IR3859M_15 Datasheet, PDF (30/35 Pages) International Rectifier – HIGHLY EFFICIENT INTEGRATED 9A, SYNCHRONOUS BUCK REGULATOR

PD-97514
IR3859MPbF
Layout Considerations
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with less than expected results.
Make all the connections for the power
components in the top layer with wide, copper
filled areas or polygons. In general, it is desirable
to make proper use of power planes and
polygons for power distribution and heat
dissipation.
The inductor, output capacitors and the IR3859
should be as close to each other as possible.
This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor directly at
the Vin pin of IR3859.
The feedback part of the system should be kept
away from the inductor and other noise sources.
The critical bypass components such as
capacitors for Vcc should be close to their
respective pins. It is important to place the
feedback components including feedback
resistors and compensation components close to
Fb and Comp pins.
The connection between the OCSet resistor and
the SW pin should not share any trace with the
connection between the bootstrap capacitor and
the SW pin. Instead, it is recommended to use a
Vin _PGnd ^{Kelvin connection of the trace from the OCSet}
resistor and the trace from the bootstrap
capacito^Vrⁱⁿat the SW pin. ^PGnd
In a multilayer PCB use one layer as a power
AGnd ^{Vout ground plane and have a control circuit ground}
(analog ground), to which all signals are
referenced. The goal is to localize the high
current path to a separate loop that does not
inte_Ar_Gfe_nr_de with the more sensit^Viv^oe^ut analog control
function. These two grounds must be connected
together on the PC board layout at a single point.
The Power QFN is a thermally enhanced
package. Based on thermal performance it is
recommended to use at least a 4-layers PCB. To
effectively remove heat from the device the
exposed pad should be connected to the ground
plane using vias. Figure 28 illustrates the
implementation of the layout guidelines outlined
above, on the IRDC3859 4 layer demoboard.
Compensation parts
should be placed as close
as possible to
the Comp pin.
Vin
PGnd
Resistors Rt, SS cap,
and Rocset should be
placed as close as
possible to their pins.
AGnd
Vout
Fig. 28a. IRDC3859 demoboard layout
considerations – Top Layer
Enough copper &
minimum length
ground path between
Input and Output
All bypass caps should
be placed as close as
possible to their
connecting pins.
30
Rev 5.0