IR3088 Datasheet, PDF (30/34 Pages) International Rectifier – XPHASE PHASE IC WITH FAULT AND OVERTEMP DETECT

I
IR3088
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
• Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and
power ground plane (PGND).
• Connect PGND to LGND pins of each phase IC to the ground tab, which is tied to LGND and PGND planes
respectively through vias.
• In order to reduce the noise coupled to SCOMP pin of phase IC, use a dedicated wire to connect the capacitor
CSCOMP directly to LGND pin. However, connect PWM ramp capacitor CPWMRMP, phase delay programming
resistor RPHASE2 or RPHASE3, decoupling capacitor CVCC to LGND plane through vias.
• Place current sense resistors and capacitors (RCS+, RCS-, CCS+, and CCS-) close to phase IC. Use Kelvin
connection for the inductor current sense wires, but separate the two wires by ground polygon. The wire from
the inductor terminal to RCS- should not cross over the fast transition nodes, i.e. switching nodes, gate drive
outputs and bootstrap nodes.
• Place the decoupling capacitors CVCC and CVCCL as close as possible to VCC and VCCL pins of the phase IC
respectively.
• Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of
the gate drive paths.
• Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Use
combination of different packages of ceramic capacitors.
• There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output
capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load.
Route the switching power paths using wide and short traces or polygons; use multiple vias for connections
between layers.
LGND
PLANE
To LGND
To VIN Plane
To Signal Bus
To LGND
Plane
To Gate
Drive
Voltage
To LGND CVCC
Plane
To PGND
Plane
CVCCL
SCOMP
EAIN
PWMRMP
LGND
VCC
BIASIN
DACIN
PHSFLT
CSIN-
CSIN+
PGND
PLANE
Page 30 of 34
To Bottom To Top
MOSFET MOSFET
To
Switching
Node
Ground
Polygon
Ground
Polygon
To Inductor
9/30/04