IR2213PBF Datasheet, PDF (3/18 Pages) International Rectifier – High and Low Side Driver

IR2213(S)PBF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are
measured under board mounted and still air conditions.
Symbol
V_B
V_S
V_HO
V_CC
V_LO
V_DD
V_SS
V_IN
dVs/dt
P_D
R_THJA
T_J
T_S
T_L
Definition
High Side Floating Supply Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
Allowable Offset Supply Voltage Transient (Figure 2)
Package Power Dissipation
@ T_A ≤ +25˚C
@_TheT_rAm≥_al+_R2_e5_s°_iC_{stance, Junction to}
Ambient
(14 Lead PIDP)
(16 Lead SOIC)
(1₍4₁₄Le_La_ead_dP_PD_DI_IP_P)₎
(1₍4₁₆Le_Lea_ad_dP_SD_OI_IP_C)₎
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Min.
-0.3
V_B - 25
V_S - 0.3
-0.3
-0.3
-0.3
V_CC - 25
V_SS - 0.3
—
—
—
—
—
—
-55
—
Max.
1225
V_B + 0.3
V_B + 0.3
25
V_CC + 0.3
V_SS + 25
V_CC + 0.3
V_DD + 0.3
50
1.6
1.25
75
100
125
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The Input / Output logic timing diagram is shown in Figure 1. For proper operation the device should be used
within the recommended conditions. The V_S and V_SS offset ratings are tested with all supplies biased at 15 V
differential.
Symbol
V_B
V_S
V_HO
V_CC
V_LO
V_DD
V_SS
V_IN
Definition
High Side Floating Supply Absolute Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Logic Supply Voltage
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN & SD)
Min.
V_S + 12
†
V_S
12
0
V_SS + 3
-5 ^††
V_SS
Max.
V_S + 20
1200
V_B
20
V_CC
V_SS + 20
5
V_DD
Units
V
† Logic operational for VS of -5 to +1200V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-
3 for more details).
†† When VDD<5V, the minimum VSS offset is limited to -VDD
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February 4, 2014