IR3502_09 Datasheet, PDF (26/39 Pages) International Rectifier – XPHASE3TM CONTROL IC

IR3502
DESIGN PROCEDURES - IR3502 AND IR3507 CHIPSET
IR3502 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
The oscillator of IR502 generates square-wave pulses to synchronize the phase ICs. The switching frequency of
the each phase converter equals the PHSOUT frequency, which is set by the external resistor ROSC according to
the curve in Figure 18. The CLKOUT frequency equals the switching frequency multiplied by the phase number.
The Rosc sets the reference current used for no load offset which is given by Figure 19 and equals:
ISETPT = ^0.595
(1)
Rosc
Soft Start Capacitor CSS/DEL
The soft start capacitor CSS/DEL programs five different time parameters. They include soft start delay time, soft
start time, VID sample delay time, VR ready delay time and over-current fault latch delay time after VR ready.
For the converter using VID with boot voltage, the SS/DEL pin voltage controls the slew rate of the converter
output voltage, as shown in Figure 9. After the ENABLE pin voltage rises above 0.85V, there is a soft-start delay
time TD1, after which the error amplifier output is released to allow the soft start of output voltage. The soft start
time TD2 represents the time during which converter voltage rises from zero to 1.1V. The VID sample delay time
(TD3) is the time period when VID stays at boot voltage of 1.1V. VID rise or fall time (TD4) is the time when VID
changes from boot voltage to the final voltage. The VR ready delay time (TD5) is the time period from VR
reaching the final voltage to the VR ready signal being issued, which is determined by the delay comparator
threshold.
CSS/DEL = 0.1uF meets all the specifications of TD1 to TD5, which are determined by (2) to (6) respectively.
TD1 = ^{CSS / DEL *1.4} = ^{CSS / DEL *1.4}
I _CHG
52.5 *10 ^−6
(2)
TD2 = ^{CSS / DEL *1.1} = ^{CSS / DEL *1.1}
I _CHG
52.5 *10 ^−6
(3)
TD 3
=
C _{SS / DEL}
* (3 −1.4
I _CHG
− 1.1)
=
C_{SS / DEL} * 0.7
52.5 *10^−6
(4)
TD4 =
C _{SS / DEL} * V_DAC
I _CHG
−1.1
=
C _{SS / DEL} * V_DAC
52.5*10 ^−6
− 1.1
(5)
TD5
=
C_{SS / DEL} * (3.92
I _CHG
−
3)
− TD4
=
C_{SS / DEL} * 0.92
52.5 *10^−6
− TD4
(6)
Page 26 of 39
July 28, 2009