IR3827 Datasheet, PDF (24/44 Pages) International Rectifier – 6A Highly Integrated SupIRBuck Single-Input Voltage, Synchronous Buck Regulator

soft start signal will be pulled low. The converter
goes into hiccup mode with some hiccup blanking
time as shown in Figure 18. The convertor stays in
this mode until the over load or short circuit is
removed. With different SS_Select configurations,
the hiccup blanking time is different. Please refer to
the electrical table for details. The actual DC output
current limit point will be greater than the valley point
by an amount equal to approximately half of peak to
peak inductor ripple current.
I _OCP
=
I _LIMIT
+
∆i
2
I_OCP= DC current limit hiccup point
I_LIMIT= Over current limit (Valley of Inductor Current)
Δi= Peak-to-peak inductor ripple current
IL
0
HDrv
0
LDrv
0
PGood
0
Over Current Limit
Hiccup Blanking Time
...
...
Figure 18 Timing Diagram for Hiccup Over Current
Protection
Over current limit is affected by the V_CC voltage. For
some single rail operations where V_in is 5V or less,
the OCP limit will de-rated due to the drop of V_CC
voltage. Figure 19 and Figure 20 show the over
current limit for two single rail applications with
V_in=PV_in=5V and V_in=PV_in=V_CC=4.5V respectively.
Figure 19 OCP Limit at V_in=PV_in=5V using Internal LDO
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IR3827
Figure 20 OCP Limit at V_in=PV_in=V_CC=4.5V
OVER-VOLTAGE PROTECTION (OVP)
Over-voltage protection in IR3827 is achieved by
comparing FB pin voltage to a pre-set threshold.
OVP threshold is set at 1.2×Vref. When FB pin
voltage exceeds the over voltage threshold, an over
voltage trip signal asserts after 2us (typ.) delay.
Then the high side drive signal HDrv is turned off
immediately, PGood flags low. The sync FET
remains on to discharge the output capacitor. When
the V_FB voltage drops below the threshold, the sync
FET turns off to prevent the complete depletion of
the output capacitor. After that, HDrv remains off
until a reset is performed by cycling either V_cc or
Enable. Figure 21 shows the timing diagram for over
voltage protection. Please note that OVP
comparator becomes active only when the IR3827 is
enabled.
POWER GOOD OUTPUT
IR3827 continually monitors the output voltage via
FB voltage. The FB voltage is an input to the window
comparator with upper and lower threshold of 120%
and 85% of the reference voltage respectively.
PGood signal is high whenever FB voltage is within
the PGood comparator window thresholds. For pre-
biased start-up, PGood is not active until the first
gate signal of the control FET is generated.
The PGood pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation.
In addition, PGood is also gated by other faults
including over current and over temperature. When
July 18, 2013