IRS2336 Datasheet, PDF (20/47 Pages) International Rectifier – HIGH VOLTAGE 3 PHASE GATE DRIVER IC

IRS2336x(D) Family
Figure 5: Input/output timing diagram for the IRS2336xD family
ITRIP
FAULT
RCIN
HOx
VIT,TH+
Interval B Interval C
VIT,TH-
50%
tFLT
50%
VRCIN,TH
tITRIP
90%
tFLTCLR
Figure 6: Detailed view of B & C intervals
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs
within IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts
a time period (a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to
ensure that the power switch being turned off has fully turned off before the second power switch is turned on. This
minimum deadtime is automatically inserted whenever the external deadtime is shorter than DT; external deadtimes
larger than DT are not modified by the gate driver. Figure 7 illustrates the deadtime period and the relationship
between the output gate signals.
The deadtime circuitry of the IRS2336xD is matched with respect to the high- and low-side outputs of a given
channel; additionally, the deadtimes of each of the three channels are matched. Figure 7 defines the two deadtime
parameters (i.e., DT₁ and DT₂) of a specific channel; the deadtime matching parameter (MDT) associated with the
IRS2336xD specifies the maximum difference between DT₁ and DT₂. The MDT parameter also applies when
comparing the DT of one channel of the IRS2336xD to that of another.
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