IR3831MPBF Datasheet, PDF (20/31 Pages) International Rectifier – HIGHLY EFFICIENT INTEGRATED SYNCHRONOUS BUCK REGULATOR FOR DDR APPLICATIONS

IR3831MPbF
ZIN
VOUT
C7
R10
R8
C3
R3
C4
Zf
Fb _E/A
R9
Gain(dB)
VREF
H(s) dB
Ve
Comp
FZ1 FZ2
FP2
FP3 ^Frequency
Fig.14. Type III Compensation network and
its asymptotic gain plot
The compensation network has three poles and
two zeros and they are expressed as follows:
F_P1 = 0............................................................(26)
F_P2
=
2π
1
* R₁₀
* C₇
...........................................(27)
F_P3
=
2π
1
*
R₃
⎜⎜⎝⎛
C₄
C₄
* C₃
+ C₃
⎟⎟⎠⎞
≅
2π
1
* R₃
* C₃
.......... ....(28)
F_Z1
=
2π
*
1
R₃
* C₄
.........................................(29)
F_Z2
=
2π
* C₇
1
* (R₈
+ R₁₀ )
≅
2π
1
* C₇
* R₈
..........(30)
Cross over frequency is expressed as:
F_o
= R₃
* C₇
* ^Vin
V_osc
*
2π
1
* L_o
* C_o
................................(31)
Based on the frequency of the zero generated by
the output capacitor and its ESR, relative to
crossover frequency, the compensation type can
be different. The table below shows the
compensation types and location of the
crossover frequency.
11/05/10
Compensator
Type
F_ESR vs F_o
Output
Capacitor
Type II
Electrolytic
F_LC<F_ESR<F_o<F_s/2 _Tantalum
Type III
F_LC<F_o<F_ESR
Tantalum
Ceramic
The higher the crossover frequency, the
potentially faster the load transient response.
However, the crossover frequency should be low
enough to allow attenuation of switching noise.
Typically, the control loop bandwidth or crossover
frequency is selected such that
F_o ≤ (1/5~1/10) * F_s
The DC gain should be large enough to provide
high DC-regulation accuracy. The phase margin
should be greater than 45^o for overall stability.
For this design we have:
V_in=12V
V_o=0.75V
V_osc=1.8V
Vp=0.75V
L_o=0.6 uH
C_o=8x22uF, ESR=3mOhm each
It must be noted here that the value of the
capacitance used in the compensator design
must be the small signal value. For instance, the
small signal capacitance of the 22uF capacitor
used in this design is 12uF at 0.75 VDC bias and
400 kHz frequency. It is this value that must be
used for all computations related to the
compensation. The small signal value may be
obtained from the manufacturer’s datasheets,
design tools or SPICE models. Alternatively, they
may also be inferred from measuring the power
stage transfer function of the converter and
measuring the double pole frequency F_LC and
using equation (16) to compute the small signal
C_o.
These result to:
F_LC=20.97 kHz
F_ESR=4.4 MHz
F_s/2=200 kHz
Select crossover frequency: F_o= 60 kHz
Since F_LC<F_o<F_s/2<F_ESR, TypeIII is selected to
place the pole and zeros.
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