IR3899 Datasheet, PDF (18/43 Pages) International Rectifier – 9A HIGHLY INTEGRATED SUPLRBUCK

9A Highly Integrated SupIRBuck^TM
Single‐Input V_-o₁lt₈a_-ge, Synchronous Buck Regulator
PD‐97661
IR3899
Pvin(12V)
Vcc
Vp>1V
Enable >1.2V
Intl_SS
Figure 5a: Recommended startup for Normal operation
Pvin (12V)
Vcc
Enable> 1. 2 V
Intl_SS
Vp
Figure 5b: Recommended startup for sequencing operation
(ratiometric or simultaneous)
Pvin (12V)
Figure 5a shows the recommended start‐up sequence for
the normal (non‐tracking, non‐sequencing) operation of
IR3899, when Enable is used as a logic input. Figure 5b
shows the recommended startup sequence for sequenced
operation of IR3899 with Enable used as logic input. Figure
5c shows the recommended startup sequence for tracking
operation of IR3899 with Enable used as logic input.
In normal and sequencing mode operation, Vref is left
floating. A 1nF ceramic capacitor is recommended
between this pin and Gnd. In tracking mode operation,
Vref should be tied to Gnd.
It is recommended to apply the Enable signal after the VCC
voltage has been established. If the Enable signal is present
before VCC, a 50kΩ resistor can be used in series with the
Enable pin to limit the current flowing into the Enable pin.
PRE‐BIAS STARTUP
IR3899 is able to start up into pre‐charged output, which
prevents oscillation and disturbances of the output
voltage.
The output starts in asynchronous fashion and keeps the
synchronous MOSFET (Sync FET) off until the first gate
signal for control MOSFET (Ctrl FET) is generated. Figure 6a
shows a typical Pre‐Bias condition at start up. The sync FET
always starts with a narrow pulse width (12.5% of a
switching period) and gradually increases its duty cycle
with a step of 12.5% until it reaches the steady state value.
The number of these startup pulses for each step is 16 and
it’s internally programmed. Figure 6b shows the series of
16x8 startup pulses.
[V]
Vo
Vcc
Vref=0
Enable > 1. 2 V
Intl_SS
Vp
Figure 5c: Recommended startup for
memory tracking operation (Vtt‐DDR)
18 August 08, 2012 |DATA SHEET | 3.4
Pre-Bias
Voltage
[Time]
Figure 6a: Pre‐Bias startup
HDRv
LDRv
... _...
12.5% 25% ^...
... _...
16
16
...
...
87.5%
...
...
...
End of
PB
Figure 6b: Pre‐Bias startup pulses