IR3841WMPBF Datasheet, PDF (18/34 Pages) International Rectifier – HIGHLY EFFICIENT INTEGRATED 8A SYNCHRONOUS BUCK REGULATOR

Application Information
Design Example:
The following example is a typical application for
IR3841W. The application circuit is shown on
page 23.
V_in = 12 V ( 13.2V max)
V_o = 1.8 V
I_o =8 A
ΔV_o ≤ 54mV
F_s = 600 kHz
Enabling the IR3841W
As explained earlier, the precise threshold of
the Enable lends itself well to implementation of
a UVLO for the Bus Voltage.
IR3841W
Enable
V _in
R₁
R₂
For a typical Enable threshold of V_EN = 1.2 V
V_{in (min)}
*
R₂
R₁ + R₂
= V_EN
= 1.2 .......... (5)
R₂
=
R₁
V_in(
V_EN
min ) ^−
V_EN
.......... (6)
For a V_{in (min)}=10.2V, R₁=49.9K and R₂=7.5K is a
good choice.
Programming the frequency
For F_s = 600 kHz, select R_t = 23.7 kΩ, using
Table. 1.
Output Voltage Programming
Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier, which
is internally referenced to 0.7V. The divider is
ratioed to provide 0.7V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:
V_o
= V_ref
∗ _{⎜⎜⎝⎛}1+
R₈
R₉
⎟⎟⎠⎞
................................(7)
Rev 5.0
IR3841WMPbF
When an external resistor divider is connected to
the output as shown in figure 11.
Equation (5) can be rewritten as:
R₉
=
R₈
∗
⎜⎜⎝⎛_V
V_ref
o^−Vref
⎟⎟⎠⎞
...............................(8)
For the calculated values of R8 and R9 see
feedback compensation section.
I_IR_R3₃8₆4₂1₄W
Fb
VOUT
R8
R9
Fig. 11. Typical application of the IR3841W for
programming the output voltage
Soft-Start Programming
The soft-start timing can be programmed by
selecting the soft-start capacitance value. From
(1), for a desired start-up time of the converter,
the soft start capacitor can be calculated by
using:
C_SS (μF) = T_start ( ms ) × 0.02857 .......... (9)
Where T_start is the desired start-up time (ms).
For a start-up time of 3.5ms, the soft-start
capacitor will be 0.099μF. Choose a 0.1μF
ceramic capacitor.
Bootstrap Capacitor Selection
To drive the Control FET, it is necessary to
supply a gate voltage at least 4V greater than
the voltage at the SW pin, which is connected
the source of the Control FET . This is achieved
by using a bootstrap configuration, which
comprises the internal bootstrap diode and an
external bootstrap capacitor (C6) as shown in
Fig. 12. The operation of the circuit is as follows:
When the lower MOSFET is turned on, the
capacitor node connected to SW is pulled down
to ground. The capacitor charges towards V_cc
through the internal bootstrap diode, which has a
forward voltage drop V_D. The voltage V_c across
the bootstrap capacitor C6 is approximately
given as
V_c ≅ V_cc − V_D .......................... (10)
When the upper MOSFET turns on in the next
cycle, the capacitor node connected to SW rises
to the bus voltage V_in. However, if the value of
C6 is appropriately chosen,
18