IR3856M_15 Datasheet, PDF (17/35 Pages) International Rectifier – HIGHLY EFFICIENT INTEGRATED 6A, SYNCHRONOUS BUCK REGULATOR

PD-97528
IR3856MPbF
TIMING DIAGRAM OF Over Voltage Protection
Fig.10 IR3856 Over Voltage Timing Diagram
External Synchronization
The IR3856 incorporates an internal circuit which
enables synchronization of the internal oscillator
(using rising edge) to an external clock. An
external resistor from Rt pin to Gnd is still
required to set the free-running frequency close
to the Sync input frequency. This function is
important to avoid sub-harmonic oscillations due
to beat frequency for embedded systems when
multiple POL (point of load) regulators are used.
The synchronization clock can be applied during
IR3856 normal operation or before IR3856 start-
up. In any case, IR3856 will perform with the
external after the end of the PreBias cycle.
Applying the external signal to the Sync input
changes the effective value of the ramp signal
(Vramp/Vosc).
V_{osc( eff )} = 1.8 × f_{Free _Run} f_Sync ........................ (5)
Equation (5) shows that the effective amplitude
of the ramp (V_osc(eff)) is reduced after the external
Sync signal is applied. More difference between
the frequency of the Sync (f_Sync) and the free-
running frequency (f_{Free_Run}) results in more
change in the effective amplitude of the ramp
signal.
Therefore, since the ramp amplitude takes part in
calculating the loop-gain and bandwidth of the
regulator, it is recommended not to use a Sync
frequency which is much higher than the free-
running frequency. In addition, the effective value
of the ramp signal, given by equation (5), should
be used when the compensator is designed for
the regulator.
The pulse width of the external clock, which is
applied to the sync, should be greater than 100ns
and its high level should be greater than 2V,
while its lower level is less than 0.6V. If this pin is
left floating, the IC will run with the free running
frequency set by the resistor Rt.
17
Rev 4.0