IRS25401PBF_15 Datasheet, PDF (14/20 Pages) International Rectifier – LED BUCK REGULATOR CONTROL IC

100
90
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10
0
0
Enable Duty Cycle Relationship to Light Output
10
20
30
40
50
60
70
80
90
100
Percentage of Light Output
Fig.5 Light Output vs Enable Pin Duty Cycle
EN
HO
IRS254(0,1)(S)PbF
to form the voltage clamp. The repetition of the
spikes can be reduced by simply increasing the
capacitor size.
The two resistors form a voltage divider for the
output, which is then fed into the cathode of the zener
diode. The diode will only conduct, flooding the
enable pin, when its nominal voltage is exceeded.
The chip will enter a disabled state once the divider
network produces a voltage at least 2.5 V greater
than the zener rating. The capacitor serves only to
filter and slow the transients/switching at the positive
output terminal. The clamped output voltage can be
determined by the following analysis. The choice of
capacitor is at the designer’s discretion.
This scheme will not be adequate in all applications.
An improved method is described in IRPLLED1 Rev
D reference design documentation.
V_out
=
(2.5V
+ DZ )(R₁
R₂
+
R₂ )
DZ = Zener Diode Nominal Rated Voltage
LO
Fig.6 IRS254(01,11) Dimming Signals
Open Circuit Protection Mode
There are several
Vout
methods of providing
over voltage protection
R1
at the output if needed.
The following very
simple method uses a
IFB
3
voltage
divider,
capacitor, and zener
EN
4
R2
diode, the output
voltage can be clamped
Fig.7 Open Circuit
at any desired value. In open- ^{Protection Scheme}
circuit condition without any
output clamp, the positive output terminal may reach a
high DC voltage. Switching will still occur between the
HO and LO outputs, whether due to the output voltage
clamp or the watchdog timer. Transients and switching
will be observed at the positive output terminal as seen
in Fig. 8. The difference in signal shape, between the
output voltage and the I_FB, is due to the capacitor used
Fig.8 Open Circuit Fault Signals, with Clamp
Under-voltage Lock-out Mode
The under-voltage lock-out mode (UVLO) is defined
as the state IRS254(01,11) is in when _VCC is below
the turn-on threshold of the IC. During startup
conditions, if the IC supply remains below _V , _CCUV+ the
IRS254(01,11) will enter the UVLO mode. This state
is very similar to when the IC has been disabled via
control signals, except that LO is also held low.
When the supply is increased to , V_CCUV+ the IC enters
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